IC Design Interview 6: Op-amp Circuits

You must know your op-amp circuits to do analog circuit design! During an interview, you even have to derive the operation equations. Each of these derivations starts with the result in bold (because you must just know that) followed by the derivation.

Inverting Op-Amp

V_out = -(R₂/R₁)V_in

V_in/R₁ = -V_out/R₂
-(R₂/R₁)V_in = V_out

Non-Inverting Op-Amp (Buffer)

V_out = V_in(1+R₁/R₂) = V_in((R₂+R₁)/R₂)

V- = V_out R₂/(R₂+R₁)  [Voltage Divider]
Assume V- = V_in
V_in = V_out R₂/(R₂+R₁)
(R₂+R₁)/R₂ V_in = V_out
The special case of R₂ being open (infinite resistance) creates a Unity Gain Buffer

Difference Amplifier

V_out = R₂/R₁ (V_B-V_A)

Assume V- = V+
V+ = V_B R₂/(R₁+R₂)   [Voltage Divider]
Since I₁=I₂                 [Kirchoff's Current Law]
(V_out-V-)/R₂ = (V--V_A)/R₁
Solve for V-
R₁V_out+R₂V_A = V-
      R₂+R₁
Which is the same as V+, so
R₁V_out+R₂V_A = V_B R₂
      R₂+R₁             R₁+R₂
Which can be solved for V_out
                                                                                         V_out = R₂/R₁ (V_B-V_A)

IC Design Interview 7: Buck Regulator

Buck DC-DC Switch Mode Power Supply (SMPS) come up in interviews quite a bit these days. Here is my quick review sheet. You may want to be careful it; I bombed the interview I prepared it for.

The obvious things about a buck regulator need to be said. A buck regulator can only translate an input voltage to a lower voltage, never a higher voltage; that requires a boost regulator. The current through an inductor may not change instantly. The voltage across an inductor may change "instantly". 

I sometimes think of a buck regulator as a filter placed on a pulse width modulated (PWM) signal. The output is then simply the average value the voltage before the inductor/capacitor filter. This analogy is not acceptable to most engineers who actually design these circuits. 

Figure 1. Buck regulator overview.

The diode is almost always implemented as a transistor. The transistor that replaces the diode is turned on when the other transistor is turned off. They must not both be on at the same time. If they are both on, significant current shoots through from the input power straight to ground through them. 

Figure 2. Current through and voltage across the inductor.

V = L di/dt        the basic inductor equation
V/L dt = di        just pretend you can do that with derivatives
∫ V/L dt = ∆I     the integration is to t_on
(V_on-V_n)/L t_on = ∆I

The area under the voltage curve (V_n-V_o)*t_on is the same same as the area over the rest of the voltage curve -V_o*(t_off-t_on). That is the same as saying the energy into and out of the inductor is the same.

IC Design Interview 5: Latch-up

IC Design Interview 4 is the Folded Cascode Op-amp. I don't have it ready yet, so I'm moving on to latch-up.


Preventing latch-up is easy, until it isn't. The guidelines are to tie the substrate to the lowest potential on the chip and the n-wells to the highest potential on the chip. And tie them well. In metal. As often as practical. Easy enough. Except for that input pair whose well isn't tied to the supply. Or the chips with multiple supplies.

It helps to understand what is happening in the chip during latch-up. Devices you didn't put in there are poking their very real heads up and saying, "Boo!" The diagrams below show the parasitic devices in red superimposed over the devices that are supposed to be there. Notice that you cannot make the parasitic devices go away, you can only make them not turn on.

Latch-up will occur if

• supplies can sustain latch-up current
• loop gain ≳ 1, i.e., β_npnβ_pnp ≳ 1
• Base-Emitter junction forward biased

The BE junction will forward bias if

• either drain taken beyond its respective supply
• the current or resistor is large enough to create a large voltage drop 

The usual line of attack is to keep those resistors as small as possible. This is usually relegated as a layout task. A good layout person will do a good job with it. As a designer, you have to review the layout and verify it occurred. There should be a ring of n+ tied to the power supply surrounding each well. There should be a ring of p+ tied to ground surrounding each substrate region.  The substrate and well ties do not generally require much DC current. You may be able to make the ties on separate metal runs from the active supplies. Do so if you're allowed to. Don't be afraid to separate wells tied to different potentials by a bit more than the required distance.

It is sometimes possible to insert a resistor in the supply path so the supply can not sustain the latch-up current. This actually can work in very low power chips where a fairly large resistor has a low voltage drop. This isn't usually an option, but I have seen it work. 

Random tip from my current day job.
The time printing via the Verilog %t format can be made more human readable by using the $timeformat command. For example, $timeformat(-6, 3, "us", 13); placed inside a begin-end block makes my job easier.

Until next week,
Bruce

IC Design Interview 3: Bandgap Reference

Life has intruded so not much update on the boost converter. I do now understand there is a brand new shiny zero that has to be taken care of. I also now understand the gate drive needs to forced to oscillate at some duty cycle regardless of the output value. I need to rework the feedback compensator to account for the boost AC characteristics instead of the buck that is in there now. Until I have that ready, here's some more interview notes.


The bandgap equations must be derived sometime during every integrated circuit design interview. At least it seems that way. It is a standard, useful circuit found in nearly every chip. I think the discussions about the circuit are better able to gauge a candidate's knowledge and experience, though. 

Start with a schematic like the one shown below. 

That last equation isn't the final answer, though I've never been asked in an interview to go beyond it. V_BE has a negative temperature coefficient and the V_T has a positive temperature coefficient so appropriate values of resistors and bipolar multipliers can be found.In general R₁ and R₂ are made equal. Then the bipolar multipliers are set based on layout. Pick a rectangular array that allows Q₁ and Q₂ to be arranged in a common centroid configuration. Then set the ratio of R₁ and R₂ for zero temperature coefficient.

There are at least four other sub-topics that I will put off until a later blog entry.

• Current conveyor instead of an op-amp
• Lower voltage reference
• Producing a VPTAT (Voltage Proportional To Absolute Temperature)
• Start-up issues

Bruce McLaren

IC Design Interview 2: Miller Op-Amp

I sprinkle Miller op-amps around my designs. They are useful to drive low capacitance internal signal lines. They make fine buffer amplifiers. Many IC designers seem to be dead set against them, but I think they do have their place. Even those engineers who would never use a Miller op-amp and spend a fair amount of time during the interview explaining why no one should ever use them will expect good knowledge of the structure, theory, and practice of design and use of the lowly Miller op-amp.

These are my interview notes so they only cover the things I tend to forget, i.e., the equations.

I am hoping to have interior trailer lights ready for next week.

Bruce McLaren

IC Design Interview 1: Basic Device Equations

I've been on both sides of the hiring desk and can say that interviewing for an IC design position is an interesting process. There aren't really that many of us, so we either know each other or know someone who knows the other. Everyone involved (the hiring manager, job seeker, other designers) is busy with things other than the interview. 

The usual process is for an interviewer to meet with the job seeker for an hour or so. This repeats about six times with a break for a group lunch. The interview is usually extremely technical in nature. There will be equations derived and schematics drawn. This seems to surprise people in other professions. 

I memorize equations poorly. This is bad when I know I will be required to recite a multitude of equations. These equations are basic to our profession and are used regularly, I just can't spit them out during an interview. So I spend several days ahead of the interview cramming as if for a test. I have prepared seven pages of basic information to be memorized before an interview with a few pages that I add on depending on the specific position. The first page of notes are the basic device equations. I present these here without explanation; the explanation would encompass an undergraduate electronics course.

I am still learning how to use google docs and embed the result in this blog.

Until next week.

Bruce McLaren