IC Design Interview 6: Op-amp Circuits

You must know your op-amp circuits to do analog circuit design! During an interview, you even have to derive the operation equations. Each of these derivations starts with the result in bold (because you must just know that) followed by the derivation.

Inverting Op-Amp

V_out = -(R₂/R₁)V_in

V_in/R₁ = -V_out/R₂
-(R₂/R₁)V_in = V_out

Non-Inverting Op-Amp (Buffer)

V_out = V_in(1+R₁/R₂) = V_in((R₂+R₁)/R₂)

V- = V_out R₂/(R₂+R₁)  [Voltage Divider]
Assume V- = V_in
V_in = V_out R₂/(R₂+R₁)
(R₂+R₁)/R₂ V_in = V_out
The special case of R₂ being open (infinite resistance) creates a Unity Gain Buffer

Difference Amplifier

V_out = R₂/R₁ (V_B-V_A)

Assume V- = V+
V+ = V_B R₂/(R₁+R₂)   [Voltage Divider]
Since I₁=I₂                 [Kirchoff's Current Law]
(V_out-V-)/R₂ = (V--V_A)/R₁
Solve for V-
R₁V_out+R₂V_A = V-
      R₂+R₁
Which is the same as V+, so
R₁V_out+R₂V_A = V_B R₂
      R₂+R₁             R₁+R₂
Which can be solved for V_out
                                                                                         V_out = R₂/R₁ (V_B-V_A)

IC Design Interview 7: Buck Regulator

Buck DC-DC Switch Mode Power Supply (SMPS) come up in interviews quite a bit these days. Here is my quick review sheet. You may want to be careful it; I bombed the interview I prepared it for.

The obvious things about a buck regulator need to be said. A buck regulator can only translate an input voltage to a lower voltage, never a higher voltage; that requires a boost regulator. The current through an inductor may not change instantly. The voltage across an inductor may change "instantly". 

I sometimes think of a buck regulator as a filter placed on a pulse width modulated (PWM) signal. The output is then simply the average value the voltage before the inductor/capacitor filter. This analogy is not acceptable to most engineers who actually design these circuits. 

Figure 1. Buck regulator overview.

The diode is almost always implemented as a transistor. The transistor that replaces the diode is turned on when the other transistor is turned off. They must not both be on at the same time. If they are both on, significant current shoots through from the input power straight to ground through them. 

Figure 2. Current through and voltage across the inductor.

V = L di/dt        the basic inductor equation
V/L dt = di        just pretend you can do that with derivatives
∫ V/L dt = ∆I     the integration is to t_on
(V_on-V_n)/L t_on = ∆I

The area under the voltage curve (V_n-V_o)*t_on is the same same as the area over the rest of the voltage curve -V_o*(t_off-t_on). That is the same as saying the energy into and out of the inductor is the same.

Design Notes: Op-amp Stability Analysis in SPICE

Op-amp stability analysis involves getting an DC operating point with the amplifier running normally then opening the feedback loop and getting small-signal AC information. This can be done by using a very large inductor to pass DC and block AC and a very large capacitor to pass AC and block DC, but I've only seen it done that way once (and that was just last week, go figure).
HSPICE and many of its relatives, including SmartSpice, have the ability for a resistor to have a different value depening on if the simulation is DC (like an operating point analysis) or AC. The schematic below shows a simple way to accomplish this. This even works with Cadence's analogLib res, but I have not gotten it work with Cadence's analogLib resBias. But if you have access to Cadence you probably want to use the stb analysis and skip all of this. 

The listing shown here is for Silvaco's SmartSpice. HSPICE isn't that different. 


.option

+ post=1
+ measout
+ nomod
+ unwrap=1
+ usedegrees
+ savemfiles=1
+ savemodelslog
+ ingold=1
.temp 25
.AC DEC 50 10 10000meg
.LET AC mGAIN = vdb(out)-vdb(pos)
.LET AC mGAINM = -(vdb(out)-vdb(pos))
.LET AC mPHASE = vp(out, pos)
.LET AC mPHASEM = 180+(vp(out, pos))
.MEAS AC mGANMRG FIND mGAINM WHEN mPHASE=-180
.MEAS AC mPHSMRG FIND mPHASEM WHEN mGAIN=0
.MEAS AC mUGF WHEN mGAIN=0


There have been some some health problems in my family, so this was just a quick note to keep this blog weekly. I expect to have assembly and operation notes on the LED drivers next week. 

Bruce McLaren

Triangle Wave Generator

The part of the saw-tooth wave generator has been played by an ideal voltage pulse source in my boost generator schematics and simulations. It's time to make a "real" one. 

Note that a saw-tooth wave generator can be replaced by a triangle wave generator operating at twice the frequency. Think of a triangle wave as two back-to-back saw-tooth waves. So I need a triangle wave generator operating at 200kHz. 

This little circuit took me longer than I thought it would. I've designed triangle wave oscillator on chips in the 100kHz to 1MHz range. Doing this from components and keeping the capacitors large enough that I'm not worried about stray capacitance swamping the real capacitance has been a bit of a mind-bender for me. 

Triangle Wave generator schematic

In the schematic shown above, the comparator has significant hysterisis. On an IC, I am used to implementing that circuit using two pass gates (an analog multiplexor) selecting which reference voltage to apply to the positive input of the comparator. This is a smaller, simpler solution on a CMOS chip.  Two resistors are the smaller, simpler solution on a PCB. 

The 10Ohm resistor R4 was needed to get the circuit to converge. 

I needed to select a very small minimum time step to get the circuit to simulate accurately. This will cause trouble if I integrate this circuit in with the boost simulation. 

Triangle wave generator simulation. The light blue signal third from the top is the output.

This is actually operating at 448kHz. once stray capacitance has its way on what will be a hand soldered board, I wouldn't be surprised at 400kHz. That's still twice as fast as I expected. I will gladly re-do my calculations in return for a smaller inductor. 

Bruce

Boost Regulator

My first attempt at designing a boost regulator was comical. I took what I knew about SMPS (Switched Mode Power Supply) buck regulators and applied that. Then I figured out that running a boost regulator in CCM (Continuos Conduction Mode) creates a RHPZ (Right Half Plane Zero) that is not present in the buck regulator. That creates a circuit that is not stable. Did everybody get through that pile of acronyms? Then it's time to make something that works.

There are three basic approaches that I could take. 

1) I could design it to run in DCM (Dis-continuos Conduction Mode), where the inductor is small enough that it is fully discharged before the end of the cycle and the current is drawn from the capacitor. This requires a bit of finesse in component sizing, load current specification, and feedback network setup. It could make sense for this application because the load current has a narrow expected range.

2) I could stick with CCM but roll the response off at a fairly low frequency. This works for this application because I'm driving LEDs through a current regulator. The load current will change very slowly, mostly with temperature.

3) I could make sense of this paper or similar and keep a high bandwidth while retaining CCM. That isn't needed for this application. Maybe next time. 

First, the most important stage of any design, the specification. You can't design something if you don't know what you're designing.

Parameter	Minimum	Typical	Maximum
Input Voltage	10 V	13.8 V	20 V
Output Voltage	40 V	44 V	48 V
Output current	36 mA	40 mA	44 mA

That's all that really matters. The input voltage minimum and maximum are somewhat arbitrary. The output voltage needs to be at least 40V to allow for the worst case corner, +/-10% seemed reasonable, so I set the maximum 20% higher. The frequency should be higher than 200Hz to avoid visible flicker, but I'll want much higher to keep the inductor size reasonable. 

Very simplified Bode plot for the boost control to output gain

The frequencies f_LC, f_Z, and f_ESR are from the output stage. The f_C frequency is where the feedback system will get the crossover frequency to be. The crossover frequency needs to be at least three times higher than f_LC so the peaking doesn't mess with it too much. f_C also needs to be at least ¹/₃ of the lowest f_Z. f_Z needs to be at least 10*f_LC.
Time for some numbers now.

The duty cycle is D ≈ (V_out−V_in)/V_out = 50-79%, 69% typical.

The minimum inductor size needed stay in continuous conduction mode with a 100kHz switching frequency is
L ≥ (V_out D (1−D)²)/(2 I_out f) = 156-347μH I choose 750μH.

The minimum capacitor to keep the output ripple to less than, say, 1V is
C ≥ (I_out D)/(ΔV f) = 0.035μF choose 1μF because that seperates f_LC and f_Z.

Therefore
f_LC = (1-D)/2π (LC)^1/2 = 1210-2910 Hz, 1.8k Hz typical.
f_Z = (V_out/I_out) (1-D)²/(2π L) = 10.1-58.4 kHz, 23 kHz typical.
I'll want f_C to be about 8kHz.

F_ESR = 1/(2π CR_ESR) = 320kHz (I assumed 500mΩ)

DC Gain is 20*log(V_out/((1-D)V_ramp) = 43dB.
Gain at f_C (8kHz) is about 18dB.

So the feedback compensation needs to provide a couple of zeros at about ³/₄f_LC or 1.35kHz, a couple of poles at f_ESR or 320kHz and attenuation of about -18dB at about 8kHz.

The next table summarizes this in terms of component values. I made a spread sheet to do the actual calculations.

Compensator values

Parameter	Formula	Numbers	Result	Std Value
GZ	GC-(20*Log(fZ/(3/4fLC)	-18dB-(20*10^(23kHz*0.75*1.8kHz))	-46dB
R1	picked	200kΩ	200kΩ	200kΩ
RZ2	R1*10^(GZ/20)	200kΩ*10^(-43dB/20)	1.50kΩ	1.5kΩ
CZ2	1/(2π RZ2 3/4fLC)	1/(2*3.1416*1.0kΩ*0.75*1.8kHz)	77.6nF	75F
CZ3	1/(2π R1 3/4fLC)	1/(2*3.1416*200kΩ*0.75*1.8Hz)	582pF	470pF
Cp1	1/(2π RZ2 FESR)	1/(2*3.1416*1.0kΩ*320kHz)	334pF	470pF
Rz3	1/(2π CZ2 FESR)	1/(2*3.1416*0.68μF*320kHz)	1.064kΩ	1.0kΩ

The inductor is larger than I'd like, but it is set by the basic specifications. I don't think I can easily make a triangle wave generator faster than 100kHz on a PCB (this will be a breadboard style project, no custom PCB will be purchased). Raising that frequency would allow a smaller inductor.

Schematic is below. This is obviously not the implementation schematic. I am using ideal op-amps, comparators, and saw-tooth wave generator. The resistors on the the op-amp outputs helped initial convergence. The highest value comped (the output of the feedback loop) can take is 9V. The saw-wave switches between 0V and 10V. This means the gate signal will always be switching, even when the feedback is saturated to its rail.

Simulation schematic for boost regulator.

A simulation showing typical operation is below. The current through the LED legs is in blue, the voltage output (pwr) is in green on the right axis, the inductor current is in orange on the left axis. The pwr output overshoots then settles to 44V. The currents are controlled at 18mA in each leg. Not too bad; I may want to raise the LED currents. I do not understand the quick drops to ground that the pwr signal does every now and then. When zoomed in on, they drop in one time step which suggests a simulation issue. I'm not certain of that, though. The 10V case input gets the output voltage up past 40V which meets spec, but it is no longer regulating. I'm going to call that good enough; low voltage operation works, but not well.

Simulation results for 10, 13, and 20V batteries.

Zoom in to show inductor current. I'm going to need a hefty inductor to handle 400mA continuous. 

The next steps are to find real components that can be used and design a saw-tooth generator. I will probably use a triangle wave generator running at twice the frequency. This would be trivial for me on and IC, but I haven't done it using components before. "It shouldn't be too bad." I'm still thinking through how best to ensure the triangle-wave always has a peak higher then feedback network's high saturation point. I will also need to either make a soft-start or a voltage limiter. 80V initial transient is a bit large, and I wouldn't be surprised if the real (non-simulation) peak is even higher. I am also considering removing the LM317 based current sources and instead controlling the current directly.


I found several good references while working to understand boost converter stabalization.

Loop compensation of voltage-mode boost converters This stepped through the design process in a organized and understandable fashion. If I had found this first instead of last, I would not have had much trouble.

Compensating the RHPZ in a CCM Boost Converter: the analytical way This is part three of a four part series that is pretty good, but hard to follow because the equations and figures are not in-line with the text.

DC/DC Boost Calc This is a quick and dirty component calculator.


I'm making some progress on this project. I would like to finish up the design in nest week's blog. What I expect to do is write an entry on miller op-amp compensation or ADC specifications because I need to prepare for a technical phone interview.

Bruce

IC Design Interview 5: Latch-up

IC Design Interview 4 is the Folded Cascode Op-amp. I don't have it ready yet, so I'm moving on to latch-up.


Preventing latch-up is easy, until it isn't. The guidelines are to tie the substrate to the lowest potential on the chip and the n-wells to the highest potential on the chip. And tie them well. In metal. As often as practical. Easy enough. Except for that input pair whose well isn't tied to the supply. Or the chips with multiple supplies.

It helps to understand what is happening in the chip during latch-up. Devices you didn't put in there are poking their very real heads up and saying, "Boo!" The diagrams below show the parasitic devices in red superimposed over the devices that are supposed to be there. Notice that you cannot make the parasitic devices go away, you can only make them not turn on.

Latch-up will occur if

• supplies can sustain latch-up current
• loop gain ≳ 1, i.e., β_npnβ_pnp ≳ 1
• Base-Emitter junction forward biased

The BE junction will forward bias if

• either drain taken beyond its respective supply
• the current or resistor is large enough to create a large voltage drop 

The usual line of attack is to keep those resistors as small as possible. This is usually relegated as a layout task. A good layout person will do a good job with it. As a designer, you have to review the layout and verify it occurred. There should be a ring of n+ tied to the power supply surrounding each well. There should be a ring of p+ tied to ground surrounding each substrate region.  The substrate and well ties do not generally require much DC current. You may be able to make the ties on separate metal runs from the active supplies. Do so if you're allowed to. Don't be afraid to separate wells tied to different potentials by a bit more than the required distance.

It is sometimes possible to insert a resistor in the supply path so the supply can not sustain the latch-up current. This actually can work in very low power chips where a fairly large resistor has a low voltage drop. This isn't usually an option, but I have seen it work. 

Random tip from my current day job.
The time printing via the Verilog %t format can be made more human readable by using the $timeformat command. For example, $timeformat(-6, 3, "us", 13); placed inside a begin-end block makes my job easier.

Until next week,
Bruce

IC Design Interview 3: Bandgap Reference

Life has intruded so not much update on the boost converter. I do now understand there is a brand new shiny zero that has to be taken care of. I also now understand the gate drive needs to forced to oscillate at some duty cycle regardless of the output value. I need to rework the feedback compensator to account for the boost AC characteristics instead of the buck that is in there now. Until I have that ready, here's some more interview notes.


The bandgap equations must be derived sometime during every integrated circuit design interview. At least it seems that way. It is a standard, useful circuit found in nearly every chip. I think the discussions about the circuit are better able to gauge a candidate's knowledge and experience, though. 

Start with a schematic like the one shown below. 

That last equation isn't the final answer, though I've never been asked in an interview to go beyond it. V_BE has a negative temperature coefficient and the V_T has a positive temperature coefficient so appropriate values of resistors and bipolar multipliers can be found.In general R₁ and R₂ are made equal. Then the bipolar multipliers are set based on layout. Pick a rectangular array that allows Q₁ and Q₂ to be arranged in a common centroid configuration. Then set the ratio of R₁ and R₂ for zero temperature coefficient.

There are at least four other sub-topics that I will put off until a later blog entry.

• Current conveyor instead of an op-amp
• Lower voltage reference
• Producing a VPTAT (Voltage Proportional To Absolute Temperature)
• Start-up issues

Bruce McLaren

IC Design Interview 1: Basic Device Equations

I've been on both sides of the hiring desk and can say that interviewing for an IC design position is an interesting process. There aren't really that many of us, so we either know each other or know someone who knows the other. Everyone involved (the hiring manager, job seeker, other designers) is busy with things other than the interview. 

The usual process is for an interviewer to meet with the job seeker for an hour or so. This repeats about six times with a break for a group lunch. The interview is usually extremely technical in nature. There will be equations derived and schematics drawn. This seems to surprise people in other professions. 

I memorize equations poorly. This is bad when I know I will be required to recite a multitude of equations. These equations are basic to our profession and are used regularly, I just can't spit them out during an interview. So I spend several days ahead of the interview cramming as if for a test. I have prepared seven pages of basic information to be memorized before an interview with a few pages that I add on depending on the specific position. The first page of notes are the basic device equations. I present these here without explanation; the explanation would encompass an undergraduate electronics course.

I am still learning how to use google docs and embed the result in this blog.

Until next week.

Bruce McLaren