PLL: Pieces and Parts

So let's take that PLL we talked about last time , take it apart and look at the pieces. 

Figure 1 shows the blocks in a Phase Locked Loop (PLL); it is the block diagram from last time with the phase detector (PD), charge pump (CP), and filter broken out and a few details added. There are several ways to implement each block, so I will just mention a simple implementation for each. We don't want to get too bogged down in the circuit details yet.

Figure 1. PLL block diagram.

A simple and effective phase detector is shown in figure 2. The phase detector figures out wether the  feedback clock leads or lags the reference clock and provides up and down signals to the next block (charge pump) to speed up or slow down the system.  Consider A to be the reference clock and B the feedback clock. When the feedback clock lags the reference clock like the first half of the timing diagram, the system needs to speed up, the up signal predominates over the dn (down) signal.  On the other hand, when the feedback clock leads the reference clock like the last half of the timing diagram, the system needs to slow down, the dn (down) signal predominates over the up signal.
The charge pump in the next stage will need complementary up and down signals, so the inverters to produce them are usually placed in this cell. That keeps the current spike from the output switch on the digital supply rail.
This block is sometimes referred to as a PFD (phase/frequency detector). Since the block does not detect frequency, I prefer phase detector. 

Figure 2. Phase detector detail.

Figure 3 has an semi-ideal model of a charge pump. The purpose of the charge pump is to raise the control voltage (VC) with the up signal and lower VC with the dn signal. Since the filter in the next block has a capacitor, this is accomplished by charging and discharging that capacitor with current sources. The current source and sink are always on, the switches merely direct them.
There are four conditions to consider,
when up is high and dn is low, the current source will charge the capacitor
when up is low and dn is high, the current sink will discharge the capacitor
when up and dn are both low, the filter capacitor will retain its value
when up and dn are both high, the filter capacitor should retain its value (this assumes the current source and sink are of the same value, which they should be)

Figure 3. Idealized version of a PLL charge pump.

The simplest passive filter is shown in figure 4. I will discuss why this needs to a second order filter in the next installment, when we will do actual math.

Figure 4. PLL Filter.

The voltage controlled oscillator shown in figure 5 is a simple, noisy current starved inverter ring. This is usually suitable for creating clocks for digital circuits and has a wonderfully wide operating range with reasonably low power. Don't try to use this oscillator in radio circuits. The nMOS labeled "W" is a weak nMOS, it insures there is always some current in the mirrors so the VCO never gets quite to zero frequency.
This is really a current controlled oscillator with a a voltage-to-current converter on the front. The ground for that voltage-to-current converter should be the same as the filter ground. The ground and power for the rest of the oscillator should be separate from the filter. It is common to put the VCO on an internal voltage regulator for its power supply. This block can really throw a bunch of noise around, so be careful with it. 

Figure 5. VCO.

Next time I will discuss stability and noise sources. I'm just starting another contract, but I intend to keep up the once a month posting schedule. This is supposed to simply be a transcription of my already existing notes, though I keep finding my notes acceptable as reminders of what I need to know but inadequate as explanations. 

Bruce McLaren

Triangle Wave Generator

The part of the saw-tooth wave generator has been played by an ideal voltage pulse source in my boost generator schematics and simulations. It's time to make a "real" one. 

Note that a saw-tooth wave generator can be replaced by a triangle wave generator operating at twice the frequency. Think of a triangle wave as two back-to-back saw-tooth waves. So I need a triangle wave generator operating at 200kHz. 

This little circuit took me longer than I thought it would. I've designed triangle wave oscillator on chips in the 100kHz to 1MHz range. Doing this from components and keeping the capacitors large enough that I'm not worried about stray capacitance swamping the real capacitance has been a bit of a mind-bender for me. 

Triangle Wave generator schematic

In the schematic shown above, the comparator has significant hysterisis. On an IC, I am used to implementing that circuit using two pass gates (an analog multiplexor) selecting which reference voltage to apply to the positive input of the comparator. This is a smaller, simpler solution on a CMOS chip.  Two resistors are the smaller, simpler solution on a PCB. 

The 10Ohm resistor R4 was needed to get the circuit to converge. 

I needed to select a very small minimum time step to get the circuit to simulate accurately. This will cause trouble if I integrate this circuit in with the boost simulation. 

Triangle wave generator simulation. The light blue signal third from the top is the output.

This is actually operating at 448kHz. once stray capacitance has its way on what will be a hand soldered board, I wouldn't be surprised at 400kHz. That's still twice as fast as I expected. I will gladly re-do my calculations in return for a smaller inductor. 

Bruce

IC Design Interview 5: Latch-up

IC Design Interview 4 is the Folded Cascode Op-amp. I don't have it ready yet, so I'm moving on to latch-up.


Preventing latch-up is easy, until it isn't. The guidelines are to tie the substrate to the lowest potential on the chip and the n-wells to the highest potential on the chip. And tie them well. In metal. As often as practical. Easy enough. Except for that input pair whose well isn't tied to the supply. Or the chips with multiple supplies.

It helps to understand what is happening in the chip during latch-up. Devices you didn't put in there are poking their very real heads up and saying, "Boo!" The diagrams below show the parasitic devices in red superimposed over the devices that are supposed to be there. Notice that you cannot make the parasitic devices go away, you can only make them not turn on.

Latch-up will occur if

• supplies can sustain latch-up current
• loop gain ≳ 1, i.e., β_npnβ_pnp ≳ 1
• Base-Emitter junction forward biased

The BE junction will forward bias if

• either drain taken beyond its respective supply
• the current or resistor is large enough to create a large voltage drop 

The usual line of attack is to keep those resistors as small as possible. This is usually relegated as a layout task. A good layout person will do a good job with it. As a designer, you have to review the layout and verify it occurred. There should be a ring of n+ tied to the power supply surrounding each well. There should be a ring of p+ tied to ground surrounding each substrate region.  The substrate and well ties do not generally require much DC current. You may be able to make the ties on separate metal runs from the active supplies. Do so if you're allowed to. Don't be afraid to separate wells tied to different potentials by a bit more than the required distance.

It is sometimes possible to insert a resistor in the supply path so the supply can not sustain the latch-up current. This actually can work in very low power chips where a fairly large resistor has a low voltage drop. This isn't usually an option, but I have seen it work. 

Random tip from my current day job.
The time printing via the Verilog %t format can be made more human readable by using the $timeformat command. For example, $timeformat(-6, 3, "us", 13); placed inside a begin-end block makes my job easier.

Until next week,
Bruce

IC Design Interview 3: Bandgap Reference

Life has intruded so not much update on the boost converter. I do now understand there is a brand new shiny zero that has to be taken care of. I also now understand the gate drive needs to forced to oscillate at some duty cycle regardless of the output value. I need to rework the feedback compensator to account for the boost AC characteristics instead of the buck that is in there now. Until I have that ready, here's some more interview notes.


The bandgap equations must be derived sometime during every integrated circuit design interview. At least it seems that way. It is a standard, useful circuit found in nearly every chip. I think the discussions about the circuit are better able to gauge a candidate's knowledge and experience, though. 

Start with a schematic like the one shown below. 

That last equation isn't the final answer, though I've never been asked in an interview to go beyond it. V_BE has a negative temperature coefficient and the V_T has a positive temperature coefficient so appropriate values of resistors and bipolar multipliers can be found.In general R₁ and R₂ are made equal. Then the bipolar multipliers are set based on layout. Pick a rectangular array that allows Q₁ and Q₂ to be arranged in a common centroid configuration. Then set the ratio of R₁ and R₂ for zero temperature coefficient.

There are at least four other sub-topics that I will put off until a later blog entry.

• Current conveyor instead of an op-amp
• Lower voltage reference
• Producing a VPTAT (Voltage Proportional To Absolute Temperature)
• Start-up issues

Bruce McLaren