IC Design Interview 5: Latch-up

IC Design Interview 4 is the Folded Cascode Op-amp. I don't have it ready yet, so I'm moving on to latch-up.


Preventing latch-up is easy, until it isn't. The guidelines are to tie the substrate to the lowest potential on the chip and the n-wells to the highest potential on the chip. And tie them well. In metal. As often as practical. Easy enough. Except for that input pair whose well isn't tied to the supply. Or the chips with multiple supplies.

It helps to understand what is happening in the chip during latch-up. Devices you didn't put in there are poking their very real heads up and saying, "Boo!" The diagrams below show the parasitic devices in red superimposed over the devices that are supposed to be there. Notice that you cannot make the parasitic devices go away, you can only make them not turn on.

Latch-up will occur if

• supplies can sustain latch-up current
• loop gain ≳ 1, i.e., β_npnβ_pnp ≳ 1
• Base-Emitter junction forward biased

The BE junction will forward bias if

• either drain taken beyond its respective supply
• the current or resistor is large enough to create a large voltage drop 

The usual line of attack is to keep those resistors as small as possible. This is usually relegated as a layout task. A good layout person will do a good job with it. As a designer, you have to review the layout and verify it occurred. There should be a ring of n+ tied to the power supply surrounding each well. There should be a ring of p+ tied to ground surrounding each substrate region.  The substrate and well ties do not generally require much DC current. You may be able to make the ties on separate metal runs from the active supplies. Do so if you're allowed to. Don't be afraid to separate wells tied to different potentials by a bit more than the required distance.

It is sometimes possible to insert a resistor in the supply path so the supply can not sustain the latch-up current. This actually can work in very low power chips where a fairly large resistor has a low voltage drop. This isn't usually an option, but I have seen it work. 

Random tip from my current day job.
The time printing via the Verilog %t format can be made more human readable by using the $timeformat command. For example, $timeformat(-6, 3, "us", 13); placed inside a begin-end block makes my job easier.

Until next week,
Bruce

IC Design Interview 3: Bandgap Reference

Life has intruded so not much update on the boost converter. I do now understand there is a brand new shiny zero that has to be taken care of. I also now understand the gate drive needs to forced to oscillate at some duty cycle regardless of the output value. I need to rework the feedback compensator to account for the boost AC characteristics instead of the buck that is in there now. Until I have that ready, here's some more interview notes.


The bandgap equations must be derived sometime during every integrated circuit design interview. At least it seems that way. It is a standard, useful circuit found in nearly every chip. I think the discussions about the circuit are better able to gauge a candidate's knowledge and experience, though. 

Start with a schematic like the one shown below. 

That last equation isn't the final answer, though I've never been asked in an interview to go beyond it. V_BE has a negative temperature coefficient and the V_T has a positive temperature coefficient so appropriate values of resistors and bipolar multipliers can be found.In general R₁ and R₂ are made equal. Then the bipolar multipliers are set based on layout. Pick a rectangular array that allows Q₁ and Q₂ to be arranged in a common centroid configuration. Then set the ratio of R₁ and R₂ for zero temperature coefficient.

There are at least four other sub-topics that I will put off until a later blog entry.

• Current conveyor instead of an op-amp
• Lower voltage reference
• Producing a VPTAT (Voltage Proportional To Absolute Temperature)
• Start-up issues

Bruce McLaren