Wednesday, May 29, 2013

PLL: Pieces and Parts

So let's take that PLL we talked about last time , take it apart and look at the pieces. 

Figure 1 shows the blocks in a Phase Locked Loop (PLL); it is the block diagram from last time with the phase detector (PD), charge pump (CP), and filter broken out and a few details added. There are several ways to implement each block, so I will just mention a simple implementation for each. We don't want to get too bogged down in the circuit details yet.


Figure 1. PLL block diagram.

A simple and effective phase detector is shown in figure 2. The phase detector figures out wether the  feedback clock leads or lags the reference clock and provides up and down signals to the next block (charge pump) to speed up or slow down the system.  Consider A to be the reference clock and B the feedback clock. When the feedback clock lags the reference clock like the first half of the timing diagram, the system needs to speed up, the up signal predominates over the dn (down) signal.  On the other hand, when the feedback clock leads the reference clock like the last half of the timing diagram, the system needs to slow down, the dn (down) signal predominates over the up signal.
The charge pump in the next stage will need complementary up and down signals, so the inverters to produce them are usually placed in this cell. That keeps the current spike from the output switch on the digital supply rail.
This block is sometimes referred to as a PFD (phase/frequency detector). Since the block does not detect frequency, I prefer phase detector. 

Figure 2. Phase detector detail.

Figure 3 has an semi-ideal model of a charge pump. The purpose of the charge pump is to raise the control voltage (VC) with the up signal and lower VC with the dn signal. Since the filter in the next block has a capacitor, this is accomplished by charging and discharging that capacitor with current sources. The current source and sink are always on, the switches merely direct them.
There are four conditions to consider,
when up is high and dn is low, the current source will charge the capacitor
when up is low and dn is high, the current sink will discharge the capacitor
when up and dn are both low, the filter capacitor will retain its value
when up and dn are both high, the filter capacitor should retain its value (this assumes the current source and sink are of the same value, which they should be)

Figure 3. Idealized version of a PLL charge pump.


The simplest passive filter is shown in figure 4. I will discuss why this needs to a second order filter in the next installment, when we will do actual math.

Figure 4. PLL Filter.


The voltage controlled oscillator shown in figure 5 is a simple, noisy current starved inverter ring. This is usually suitable for creating clocks for digital circuits and has a wonderfully wide operating range with reasonably low power. Don't try to use this oscillator in radio circuits. The nMOS labeled "W" is a weak nMOS, it insures there is always some current in the mirrors so the VCO never gets quite to zero frequency.
This is really a current controlled oscillator with a a voltage-to-current converter on the front. The ground for that voltage-to-current converter should be the same as the filter ground. The ground and power for the rest of the oscillator should be separate from the filter. It is common to put the VCO on an internal voltage regulator for its power supply. This block can really throw a bunch of noise around, so be careful with it. 

Figure 5. VCO.


Next time I will discuss stability and noise sources. I'm just starting another contract, but I intend to keep up the once a month posting schedule. This is supposed to simply be a transcription of my already existing notes, though I keep finding my notes acceptable as reminders of what I need to know but inadequate as explanations. 

Bruce McLaren