Wednesday, May 29, 2013

PLL: Pieces and Parts

So let's take that PLL we talked about last time , take it apart and look at the pieces. 

Figure 1 shows the blocks in a Phase Locked Loop (PLL); it is the block diagram from last time with the phase detector (PD), charge pump (CP), and filter broken out and a few details added. There are several ways to implement each block, so I will just mention a simple implementation for each. We don't want to get too bogged down in the circuit details yet.

Figure 1. PLL block diagram.

A simple and effective phase detector is shown in figure 2. The phase detector figures out wether the  feedback clock leads or lags the reference clock and provides up and down signals to the next block (charge pump) to speed up or slow down the system.  Consider A to be the reference clock and B the feedback clock. When the feedback clock lags the reference clock like the first half of the timing diagram, the system needs to speed up, the up signal predominates over the dn (down) signal.  On the other hand, when the feedback clock leads the reference clock like the last half of the timing diagram, the system needs to slow down, the dn (down) signal predominates over the up signal.
The charge pump in the next stage will need complementary up and down signals, so the inverters to produce them are usually placed in this cell. That keeps the current spike from the output switch on the digital supply rail.
This block is sometimes referred to as a PFD (phase/frequency detector). Since the block does not detect frequency, I prefer phase detector. 

Figure 2. Phase detector detail.

Figure 3 has an semi-ideal model of a charge pump. The purpose of the charge pump is to raise the control voltage (VC) with the up signal and lower VC with the dn signal. Since the filter in the next block has a capacitor, this is accomplished by charging and discharging that capacitor with current sources. The current source and sink are always on, the switches merely direct them.
There are four conditions to consider,
when up is high and dn is low, the current source will charge the capacitor
when up is low and dn is high, the current sink will discharge the capacitor
when up and dn are both low, the filter capacitor will retain its value
when up and dn are both high, the filter capacitor should retain its value (this assumes the current source and sink are of the same value, which they should be)

Figure 3. Idealized version of a PLL charge pump.

The simplest passive filter is shown in figure 4. I will discuss why this needs to a second order filter in the next installment, when we will do actual math.

Figure 4. PLL Filter.

The voltage controlled oscillator shown in figure 5 is a simple, noisy current starved inverter ring. This is usually suitable for creating clocks for digital circuits and has a wonderfully wide operating range with reasonably low power. Don't try to use this oscillator in radio circuits. The nMOS labeled "W" is a weak nMOS, it insures there is always some current in the mirrors so the VCO never gets quite to zero frequency.
This is really a current controlled oscillator with a a voltage-to-current converter on the front. The ground for that voltage-to-current converter should be the same as the filter ground. The ground and power for the rest of the oscillator should be separate from the filter. It is common to put the VCO on an internal voltage regulator for its power supply. This block can really throw a bunch of noise around, so be careful with it. 

Figure 5. VCO.

Next time I will discuss stability and noise sources. I'm just starting another contract, but I intend to keep up the once a month posting schedule. This is supposed to simply be a transcription of my already existing notes, though I keep finding my notes acceptable as reminders of what I need to know but inadequate as explanations. 

Bruce McLaren

Wednesday, May 01, 2013

PLL: Introduction

I've been thinking about PLLs (Phase Locked Loops) lately. I don't know why, it's just been where my brain has gone. So I'm going to try to write a description of a PLL that a non-expert can understand and then work my way up to the good stuff. This will likely be a three post topic.

A PLL takes in a single signal that has a frequency and puts out a signal that has a frequency that is a multiple of the input frequency. This is different than a frequency multiplier; a frequency multiplier makes harmonics of an input signal and then bandpasses just the desired harmonic as the output. The PLL system is a pretty cool example of what can be done with negative feedback. 

Basic PLL
Figure 1. Really basic PLL compared to a non-inverting op-amp.

Figure 1 shows the simplest view. The phase detector/charge pump/filter (PD/CP/Filter) compares the input and the output frequency and generates a signal (VC) related to the difference between them. That signal controls the voltage controlled oscillator (VCO) that generates the output. The frequency divider produces the feedback. For now, I'm intentionally confusing the terms phase and frequency. If you know the difference between those terms, this paragraph isn't for you anyway. If a non-inverting op-amp makes more sense to you, compare the PLL to the one at the bottom of figure 1. The resistor divider in the feedback path causes the output to be multiplied by the the divide ratio. In both circuits, the output adjusts until the input matches the feedback. That is the magic of negative feedback.

But wait, this PLL can only multiple an input frequency by an integer multiple. It can take a 10MHz reference and produce a 20MHz, 30MHz, 40MHz, etc. output. But what if I need a 25MHz output? Something I once had the opportunity to implement was a T1 clock (1.544MHz) converted to an E1 clock (2.048MHz). I've seen a couple of ways to generate odd frequency multiples. There must be a dozen other ways, some of which I've probably never heard of. What's your favorite way?

The simplest way to get a non-integer multiple is to just put a digital divider on the output as shown in figure 2. Now the feedback divider multiplies the output by N and the output divider divides it by M. To get 25MHz from 10MHz, use a divide-by-5 divider in the feedback path (N=5) and a divide-by-2 divider (M=2) in the output. Even better would be to use a divide-by-10 in the feedback and a divide-by-4 in the output; this makes it easy to keep the feedback clock with a nice 50% duty cycle. This is not strictly necessary, in general the phase detector is only paying attention to either the rising or falling edge of the feedback, but it is usually preferable to separate the edges as much as possible, i.e., 50% duty cycle. Keep in mind that using a higher divisor in the feedback means a higher frequency directly out of the VCO; there is certainly a top speed to the VCO that your circuit should not even get close to. By the way, that T1-to-E1 conversion was accomplished with a divide-by-256 in the feedback path (VCO frequency 395.264MHz) and a divide-by-193 on the output. Two posts from now, I'll discuss why such high divide ratios can give opportunities for noise (clock jitter). Of course, the divider on the output allows the output clock to be slower than the input clock. For example if N=193 and M=256, than the PLL could be an E1-to-T1 clock converter with 2.048MHz input and 1.544MHz output.

Figure 2. Simple addition to create N/M output.

The previous implementation of that T1-to-E1 frequency converter was in a process that did not allow the VCO to operate that fast so a fractional-N implementation was used like the one shown in figure 3. (I didn't do that implementation, and incredible engineer named Mark Thrower did.) The divider gets more complicated; sometimes it divides by N, sometimes it divides by N+1. For example, if the clock is divided by seven three times then divided by eight once, over and over, the output clock will be effectively divided by 7 3/4. Obviously, there will be "jumps" in the system when the divisor changes, so the filter will need to remove them.

Figure 3. Fractional-N PLL.

Another easy to explain method of generating troublesome ratios is cascade multiple PLLs with different feedback and output dividers. This method has the obvious drawback of using more circuitry. A more subtle drawback is reinforced jitter peaking which will have to wait until the math post to be discussed. It can still be a useful technique, especially when the intermediate frequency is needed for internal circuits. Figure 4 shows a contrived example starting at 10MHz and ending with 93.75Mhz and 75MHz with the VCO frequency staying below 200MHz. If the VCO frequency could go up to 750MHz, this could have been accomplished in a single step.

Figure 4. Multiple stages to keep VCO frequency down and produce multiple outputs. 

That's the end of the introduction. We are going to have to get into electronics to get any further, and I'll leave that until the next post. Next post: pieces and parts; what goes into those black boxes. After that we'll hit the math.

Bruce McLaren